Field effect transistors (FETs) can be formed in a variety of ways to serve a variety of purposes for integrated circuits and other devices. Commonly, FETs are formed as “planar” devices in many integrated circuits, i.e., as devices in which the conduction channel has width and length extending in a direction parallel to the major surface of a substrate. FETs can be formed in a semiconductor-on-insulator (SOI) layer of a substrate or in a bulk semiconductor substrate.
Frequently, FETs are formed having a non-planar conduction channel, in order to serve a special purpose. In such non-planar FETs, either the length or the width of the transistor channel is oriented in the vertical direction, that is, in a direction perpendicular to the major surface of the substrate. In one such type of device, commonly referred to as the FinFET, the width of the conduction channel is oriented in the vertical direction, while the length of the channel is oriented parallel to the major surface of the substrate. With such orientation of the channel, FinFETs can be constructed to have a larger width conduction channel than planar FETs so as to produce larger current drive than planar FETs which occupy the same amount of integrated circuit area (the area parallel to the major surface of the substrate).
As known in the art, improved circuit performance or function can often be provided by providing extra transistors. For example, in SRAM cell designs, there are known benefits to having dual pass gate devices, such as to optimize read and write configurations, and for compensating for process corners. However, as well known in the art, the cost for ICs is generally based on their die area. Accordingly, adding extra transistors to a conventional IC design adds to the cost of the circuit. Hence, it is desirable to be able to add transistors to an IC design without adding any significant additional die area and thus additional die cost.